Background
Short Biography
Rahul Bera is a Senior Researcher at Huawei Zürich Research Center, where he does research on cutting-edge CPU microarchitecture. He earned his Ph.D. from ETH Zürich in 2025, advised by Prof. Onur Mutlu. Before his Ph.D., he worked at Intel’s Processor Architecture Research Lab (PARL) and at AMD in various capacities. His current research interest lies in high-performance memory hierarchy and systems design, especially using practical on-chip machine learning policies. His works have appeared at top-tier computer architecture conferences such as ISCA, MICRO, HPCA and ASPLOS, and have been recognized with various distinctions, including the Best Paper and the Distinguished Artifact awards at ISCA, MICRO, and HPCA.
Outside of work, he likes to hike in the mountains and writes up some of those trips.
Education
(03)Sept 2019 – Dec 2025
Doctor of Science in Electrical Engineering and Information Technology
Jul 2014 – Jan 2017
Master of Technology in Computer Science
Jul 2010 – Apr 2014
Bachelor of Engineering in Computer Science
Appointments
(04)Mar 2026 – present
Senior Researcher
Mar 2023 – Aug 2023
Graduate Research Intern
Instruction elimination opportunities for power-efficient microarchitecture design.
Feb 2017 – Aug 2019
Architecture Researcher
Aggressive prefetcher design and optimization for next-generation processors; near-cache computing for efficient DNN inference in CPU.
Jul 2015 – Dec 2015
Co-op Engineer
Designing a simulation framework alternative to instruction-based tracing for evaluating extremely-threaded workloads.